1. Field of the Invention
This invention relates to semiconductor devices and more particular to a trenched field effect transistor especially suitable for low voltage switching applications.
2. Description of the Prior Art
Field effect transistors (FETs) are well known, as are metal oxide semiconductor field effect transistors (MOSFETs); such transistors are often used for power applications. There is a need for power transistors for relatively low voltage applications, i.e. typically under 50 volts, that have low current leakage blocking capability.
Examples of trench field effect transistors suitable for such applications are disclosed in xe2x80x9cComparison of Ultra Low Specific On Resistance UMOSFET Structures . . . xe2x80x9d by Syau et al., IEEE Transactions on Electron Devices, Vol. 41, No. 5, May 1994. Inter alia, this publication describes the so-called INVFET structure of present FIG. 1, which corresponds to FIG. 1(b) of the publication. Present FIG. 1 shows only a portion of a single transistor including the polysilicon (polycrystalline silicon) gate electrode 10 which in this case is N-type polysilicon which is insulated by a gate oxide layer 12 on its sides and bottom in a trench 14 and insulated on its top side by an oxide layer 18. The trench 14 extends through the N+ doped source region 22 through the P doped base region 24 and into the N+ doped drain region 26. The drain electrode 30 is formed on the underside of the drain region 26 and the source electrode 32 formed on the top side of the source region.
Also described in FIG. 1(c) of this article and shown here in present FIG. 2 is the somewhat similar so-called EXTFET which is identical to the INVFET except for having an additional Nxe2x88x92 doped drift region 36 formed underlying the P doped base region 24. For both of these devices the P base region 24 is formed by diffusion (hence does not exhibit uniform doping) and is fairly heavily doped. It is believed that a typical surface concentration of the P base region 24 is 1017/cm3.
These devices are both intended to avoid full depletion of the P base (body) region 24. They each have the gate electrode 10 doped to the same conductivity type as is the drain region 26 (i.e. N type) as shown in FIGS. 1 and 2. The xe2x80x9cmesaxe2x80x9d width, i.e. the width of the source region between two adjacent trenches, is typically 3 xcexcm and a typical cell pitch for an N-channel device is about 6 xcexcm. Blocking is accomplished by a quasi-neutral (undepleted) PN junction at a Vgs (gate source voltage) of zero. The ACCUFET (see Syau et al. article) offers the best specific on resistance at the expense of poor blocking capability, while the INVFET and EXTFET offer improved blocking at the expense of increased specific on resistance.
As is well known, a power MOSFET should have the lowest possible on-state specific resistance in order to minimize conduction losses. On-state resistance is a well known parameter of the efficiency of a power transistor and is the ratio of drain-to-source voltage to drain current when the device is fully turned on. On-state specific resistance refers to resistance times cross sectional area of the substrate carrying the drain current.
However, these prior art devices do not provide the optimum low on-state specific resistance in combination with blocking state low current leakage.
This disclosure is directed to a MOS semiconductor device suitable especially for low voltage power application where low leakage blocking capability is desirable. In accordance with the invention, the off-state blocking of a trenched field effect transistor is achieved by a gate controlled barrier region between the source and drain. Similar to the above described INVFET, forward conduction occurs through an inversion region between the source and the drain (substrate). Unlike the INVFET, however, blocking is achieved by a gate controlled depletion barrier and not by a quasi-neutral PN junction. The depletion barrier is formed and controlled laterally and vertically so as to realize the benefits of ultra-low on-state specific resistance combined with the low current leakage blocking. Advantageously, this structure is relatively easily fabricated and has blocking superior to that of prior art ACCUFET devices, with low leakage current at zero applied gate-source voltage. Moreover, in the blocking state there is no quasi-neutral PN junction, and therefore, like the ACCUFET, this structure offers the advantage of containing no parasitic bipolar PN junction.
The present device""s on-state specific resistance is comparable to that of the ACCUFET, and like the ACCUFET offers on-state specific resistance superior to that of the INVFET and EXTFET as described in the above mentioned article by Syau et al.
In an N-channel embodiment of the present invention, an N+ drain region underlies a lightly doped Pxe2x88x92 body region which is overlain by an N+ source region. The body region is formed by lightly doped epitaxy with uniform or almost uniform doping concentration, typically in a range of 1014 to 1016/cm3. The gate electrodes are formed in trenches which extend through the source region, through the body region, and partially into the drain (substrate) region. Alternatively, the gate electrodes do not extend into the drain region. The polysilicon gate electrodes themselves are P doped, i.e. having a doping type the same as that of the body region. Additionally, the mesas (holding the source regions) located between adjacent gate electrode trenches are less than 1.5 xcexcm wide, and the cell pitch is less than 3 xcexcm.
Advantageously in the blocking state the epitaxial P body region is depleted due to the applied drain-source bias Vds, and hence a punch-through type condition occurs vertically. However, lateral gate control combined with the narrow mesa width (under 1.5 xcexcm) increases the effective depletion barrier to majority carrier flow and prevents conduction. Thus, the present device is referred to herein as the PT-FET for xe2x80x9cpunch-through field effect transistorxe2x80x9d.
Thus the blocking characteristics are determined by barrier-limited majority-carrier current flow and not by avalanche breakdown. In accordance with the invention, a complementary P-channel device is implemented and has advantages comparable to those of the above described N-channel device.
The above described embodiment has a floating body region, thus allowing bidirectional operation. In another embodiment a body contact region is provided extending into the body region from the principal surface of the semiconductor structure, thus allowing a source region to body region short via the source metallization for forward blocking-only applications.
Thus advantageously the present PT-FET has a fully depleted (punch-through) lightly doped body region at a small applied drain-source voltage. This differs from the P body region in the above described INVFET and EXTFET which must, by design, be undepleted to avoid punch-through. Advantageously, the threshold voltage is low due to the lightly doped P body region and the device has an on-state specific resistance similar to that of the ACCUFET and superior to that of the INVFET or EXTFET.